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2003 Course VLSI Design

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Total No. of Questions :12] P1148 [Total No. of Pages : 2 [3864]-264 B.E. (E & T/C) VLSI DESIGN (2003 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any Three Questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary. 6) Figures to the right indicate full marks. SECTION - I Q1) a) b) Certain logic checks event, transaction on a data line. Write VHDL code for this logic. What is quiet attribute? [8] What is passive process? Explain with VHDL code for suitable logic.[8] OR Q2) a) How do you take a decision to choose modeling style of an architecture? On what factors does it depend? Suggest appropriate example. [8] b) Write VHDL code for 8 bit shift register for PISO operation. Write separate function to check clock edge. [8] Q3) a) What are the limitations of FSM? Is there any method to auto convert FSM diagram into HDL code? [8] b) Draw FSM diagram & write VHDL code for bank ATM machine. It senses a credit card insertion, four digit PIN number, five digit amount & then acknowledges to the user. [8] OR Q4) a) b) Draw state diagram for 4 digit synchronous ring counter. Write VHDL code & test bench for it. [8] How is handshaking done in UART communication? Which attributes in VHDL are useful in it? Explore with example. [8] P.T.O.

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