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2003 Course VLSI Design

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Total No. of Questions :12] P1148 [Total No. of Pages : 2 [3864]-264 B.E. (E & T/C) VLSI DESIGN (2003 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any Three Questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary. 6) Figures to the right indicate full marks. SECTION - I Q1) a) b) Certain logic checks event, transaction on a data line. Write VHDL code for this logic. What is quiet attribute? [8] What is passive process? Explain with VHDL code for suitable logic.[8] OR Q2) a) How do you take a decision to choose modeling style of an architecture? On what factors does it depend? Suggest appropriate example. [8] b) Write VHDL code for 8 bit shift register for PISO operation. Write separate function to check clock edge. [8] Q3) a) What are the limitations of FSM? Is there any method to auto convert FSM diagram into HDL code? [8] b) Draw FSM diagram & write VHDL code for bank ATM machine. It senses a credit card insertion, four digit PIN number, five digit amount & then acknowledges to the user. [8] OR Q4) a) b) Draw state diagram for 4 digit synchronous ring counter. Write VHDL code & test bench for it. [8] How is handshaking done in UART communication? Which attributes in VHDL are useful in it? Explore with example. [8] P.T.O. Q5) a) b) Q6) a) b) Q7) a) b) Q8) a) b) Q9) a) b) Q10)a) b) Q11)a) b) Q12)a) b) [3864]-264 Differentiate FPGA w. r. t. CPLD in context of architectural details. [9] What makes CPLD non volatile? Explore I/O block of CPLD in detail.[9] OR List typical technical features & specifications of any FPGA family in detail. [9] Explore the based logic & interconnect mattrix of FPGA in detail. [9] SECTION - II Why is power distribution so important? Explain the different techniques. [8] Draw the ckt diagram of SRAM/DRAM memory cell & its read, write timing diagram in detail. [8] OR What is power optimization? What are ways to achieve it? Explain in brief. [8] Give the generalized ASIC design flow & explain each step in brief. [8] Starting with voltage Transfer curve of CMOS Inverter prove that [8] Wp/Wn n/ p is needed to achieve symetry. Design CMOS logic for Y = AB + C. Compute area on chip. If this logic operates at VDD = 1 Volt, load of 10pF and output Y is changing at the rate of 10 MHz, calculate power dissipation. [8] OR What is PDP? What does designer understand from it? What is its maximum value for a logic? [8] Which different device & wiring parasitics are important in digital design? Which are dominant? [8] What is JTAG? How does boundary scan work when number of devices/ FPGAS is more than one on a board? [9] Why is testability necessary? Explain with suitable example. [9] OR What are the different faults involved in chip design? What are techniques to minimize them? [9] Explore partial scan & full scan with suitable examples in detail. [9] xxxx 2

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