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2003 Course VLSI Design (Elective II)

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Total No. of Questions : 12] [Total No. of Pages : 2 [3864] - 233 P 1065 B.E. (Electrical) VLSI DESIGN (2003 Course) (Elective - II) (403150) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any 3 questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed. 6) Assume suitable data, if necessary. SECTION - I Q1) a) b) Draw and explain 4 bit Decade Up / Down counter. Draw and explain 4 bit Universal Shift Register. [8] [8] OR Q2) a) b) Q3) a) b) i) ii) i) ii) Differentiate Mealy and Moore machine modelling. [4] Draw state diagram for 10101 detector. Use Mealy model. [4] Draw multiplexer tree to implement 16 : 1 mux using 4 : 1 mux. [4] Draw and explain 3 x 8 Decoder along with its truth-table. [4] Explain EDA tool design flow in detail. Define the following terms : i) Entity ii) Architecture iii) Configuration. [9] [9] OR Q4) a) b) Write VHDL code for 2 x 4 Decoder and also draw its functional diagram and truth table. [9] Explain various types of Architectures along with its example in VHDL. [9] P.T.O. Q5) a) b) What is a package? Explain along with its example in VHDL. Explain various data-types and data objects in VHDL. [8] [8] OR Q6) a) b) Differentiate function and procedure along with example in VHDL. [8] What is the difference between concurrent statement and sequential statements? Explain with example. [8] SECTION - II Q7) a) b) Explain the following terms w.r.t. CMOS. i) FAN in ii) FAN out iii) Power Dissipation iv) Propagation Delay. Implement basic gates using CMOS. [8] [8] OR Q8) a) b) Explain the Enhancement type MOSFET construction. Explain the voltage transfer characteristics for CMOS. [8] [8] Q9) a) b) Draw and explain the architecture of CPLD in detail. Explain the meaning of i) Simulation ii) Synthesis iii) Place & Route iv) Boundry Scan. [9] [9] OR Q10)a) b) Differentiate PLD, CPLD, FPGA. [8] With neat schematic explain the architectural building blocks of FPGA. [10] Q11)a) b) Write VHDL code for 8x 8 RAM and explain. [8] Explain in detail ALU with ADD, SUB, INC, DEC and basic logical operations. [8] OR Q12)a) b) Write down VHDL code for 8 bit binary to integer converter. [8] Draw state diagram and explain along with VHDL code 3 bit UP counter. [8] [3864] - 233 -2-

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