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2003 Course VLSI Design (Elective II)

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Total No. of Questions : 12] P943 [Total No. of Pages : 2 [3664]-190 B.E. (Electrical) VLSI DESIGN (Elective - II) (2003 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates: 1) Answer any three questions from each section. 2) Answer three questions from section-I and three questions from section-II. 3) Answers to the two sections should be written in separate books. 4) Neat diagrams must be drawn wherever necessary. 5) Figures to the right indicate full marks. 6) Assume suitable data, if necessary. SECTION - I Q1) a) Explain Mealy and Moore machine modelling with example. [10] b) Draw Mealy machine state diagram for 1011 and 0101 sequence. [8] OR Q2) a) Draw and explain universal shift register. [9] b) Draw ckt. diagram, truth table and timing diagram for 4 bit ring counter. [9] Q3) a) Write VHDL code for multiplexer 8:1 using structural and dataflow type of modelling. [8] b) Explain the terms : i) ii) iii) iv) [8] Entity. Configuration. Component. Architecture. OR Q4) a) Explain with example configuration. b) What is architecture? Explain its modelling types. Q5) a) Explain any four data types and data objects. b) Explain with example concurrent and sequential statements. [8] [8] [8] [8] P.T.O. OR Q6) a) What do you mean by subprogram? Explain with example. b) Define package and explain it in detail with VHDL example. [8] [8] SECTION - II Q7) a) Explain in detail the construction of depletion type MOSFET. b) Implement basic gates using CMOS. [8] [8] OR Q8) a) Explain the terms : i) ii) iii) iv) [8] Propagation delay. Power dissipation. Figure of merit. Fan-out. b) Draw the circuit diagram and layout of XOR gate by using CMOS. [8] Q9) a) Explain in detail the architecture of FPGA. b) Explain the difference between CPLD and FPGA. [9] [9] OR Q10) a) Explain EDA tool design flow indetail. b) Differentiate PLD, CPLD and PAL. Q11) a) Write VHDL code for comparator. b) Write VHDL code and explain 8 8 RAM. [9] [9] [8] [8] OR Q12) a) Write VHDL code for 8 bit binary to integer converter. [8] b) Write VHDL code for ALU with addition, sub, increment and decrement operation. [8] xxxx [3664]-190 2

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