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2003 Course VLSI Design

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Total No. of Questions : 12] P986 [Total No. of Pages : 2 [3664]-197 B.E. (E & T/C) VLSI DESIGN (2003 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate answer books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary. SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Q4) a) b) Write VHDL code for 8 byte RAM. Write test bench to verify write & read operations. What are the timing constraints? [8] What is need of package? Write VHDL code to explain utility of package. [8] OR Compare with suitable examples the architectural modeling techniques. [8] Write VHDL code for 16 bit bidirectional bus. [8] Why is synchronization so important in FSM? What are the methods to achieve? [8] Draw state diagram & write VHDL code for UART. [8] OR Why is state minimization required? How is it achieved? [8] Draw FSM state diagram for traffic light controller & write VHDL code for it. [8] Q5) With the help of primitive building blocks draw & explore the architecture of CPLD in detail. [18] OR Q6) What are the architectural differences between CPLD & FPGA? What is selection criterion of CPLD / FPGA in the application. Explore in detail.[18] P.T.O.

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