Trending ▼   ResFinder  

1997 Course VLSI Design (Elective)

2 pages, 23 questions, 0 questions with responses, 0 total responses,    0    0
pune_eng
   		+Fave Message
ProfileTimelineUploadsQ & A
 Home > pune_eng >

Formatting page ...

Total No. of Questions : 10] P1202 [Total No. of Pages : 2 [3664]-31 B.E. (E & T/C) VLSI DESIGN (Elective) (1997 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answers to the two sections must be written in separate answer books. 2) Answer any three questions from each section. 3) Figures to the right indicate full marks. 4) Assume suitable data where necessary and state your assumptions clearly. SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Q4) a) b) Design CMOS logic for y = ABC + D. Calculate area needed on chip. Draw the static transfer characteristics of CMOS inverter. Explain region of operations on this characteristics curve. the [8] the [8] What is RTL? What are its advantages while writing VHDL code? Give suitable examples. [8] What are merits and demerits of synchronous system design. Explain with examples. [8] What are the signal attributes available in VHDL? Explain each with an example. [8] Compare Signal and Variable. Give suitable example for each comparison. [8] Write VHDL code for Decade/binary counter with load, Up/Down, reset, CE and BCD/Binary mode of Operation controls. Write suitable testbench for the same. [12] What are the constraints in PAR? [4] Q5) Write short notes on any THREE: a) Design flow of VHDL EDA tools. b) Technology scaling in CMOS. c) JTAG. d) Static and Dynamic Hazards. [18] P.T.O.

Formatting page ...

 

  Print intermediate debugging step

Show debugging info


 


Tags : Pune, Engineering, University of Pune, Engineering question papers, Pune University, previous year question papers, question papers, india, model question paper, pune university paper pattern, pune university syllabus, old question papers  

© 2010 - 2024 ResPaper. Terms of ServiceContact Us Advertise with us

 

pune_eng chat