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1997 Course VLSI Design (Elective)

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Total No. of Questions : 10] P1202 [Total No. of Pages : 2 [3664]-31 B.E. (E & T/C) VLSI DESIGN (Elective) (1997 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answers to the two sections must be written in separate answer books. 2) Answer any three questions from each section. 3) Figures to the right indicate full marks. 4) Assume suitable data where necessary and state your assumptions clearly. SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Q4) a) b) Design CMOS logic for y = ABC + D. Calculate area needed on chip. Draw the static transfer characteristics of CMOS inverter. Explain region of operations on this characteristics curve. the [8] the [8] What is RTL? What are its advantages while writing VHDL code? Give suitable examples. [8] What are merits and demerits of synchronous system design. Explain with examples. [8] What are the signal attributes available in VHDL? Explain each with an example. [8] Compare Signal and Variable. Give suitable example for each comparison. [8] Write VHDL code for Decade/binary counter with load, Up/Down, reset, CE and BCD/Binary mode of Operation controls. Write suitable testbench for the same. [12] What are the constraints in PAR? [4] Q5) Write short notes on any THREE: a) Design flow of VHDL EDA tools. b) Technology scaling in CMOS. c) JTAG. d) Static and Dynamic Hazards. [18] P.T.O. SECTION - II Q6) Draw the architecture of FPGA. Draw in detail the Tiles, CLB, LC, GRM and IOB of the same. [16] Q7) a) What is the difference between pre-synthesis, post-synthesis and post PAR simulations. [8] b) What are the Synthesis issues in VHDL program? Explain them with suitable examples. [8] Q8) a) Explain the following statements with examples: ALIAS, ARRAY TYPE, ENTITY, Guarded signal assignment statement. [10] Compare FPGA and CPLD. [6] b) Q9) a) Write VHDL code for a rising edge triggered D flip flop with [8] asynchronous set and reset inputs and Q and Q_bar outputs. b) What is the need of configuration in VHDL? Explain configuration [8] binding with an example. Q10)Write short notes on any THREE: [18] a) Overloading in VHDL. b) Data objects in VHDL. c) Shift operators in VHDL. d) Resolution function and multiple drivers. Y [3664] - 31 2

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