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2003 Course VLSI Design

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Total No. of Questions : 12] P997 [Total No. of Pages : 2 [3664]-214 B.E. (Electronics) VLSI DESIGN (New 2003 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed. 6) Assume suitable data, if necessary. SECTION - I Q1) Write VHDL Code for mux 8 : 1 using any two modelings and also write test bench for it. [16] OR Q2) a) Explain VLSI Design Flow. [8] b) Write VHDL Code for Decoder 2 : 4. Q3) Draw SM chart and write VHDL code for VART Transmitter. [8] [16] OR Q4) By considering suitable examples, explain different techniques of state minimization. [16] Q5) Draw block diagram and explain detail architecture of CPLD. [18] OR Q6) Draw block diagram and explain detail architecture of FPGA. [18] P.T.O.

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