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1997 Course VLSI Design

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Total No. of Questions : 10] P1604 [Total No. of Pages : 2 [3764] - 1056 B.E. (Electronics) VLSI DESIGN (1997 Course) Time : 3 Hours] Instructions to the candidates: [Max. Marks : 100 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary. SECTION - I Q1) a) b) Draw the primitive building blocks of CPLD. Explore each block in detail. [12] Compare CPLD & FPGA in brief. [4] Q2) Draw FSM diagram for decade counter. Write VHDL code and Test bench.[16] Q3) a) b) Explain inertial, delta & wire delays in detail. Write VHDL code for 8 bit shift register for SIPO operation. [8] [8] Q4) Draw & explain high level ASIC design flow in detail. Mention the input & output files in each step. [16] Q5) Write short notes on (any three): a) Passive process. b) Interconnect matrix. c) Power dissipations in CMOS. d) Voltage transfer curve of CMOS Inverter. e) Power delay product. [18] P.T.O. SECTION - II Q6) a) b) What are the types of test benches? Explain with examples. Explore any two attributes in VHDL with suitable examples. [8] [8] Q7) a) b) What are the advance tools for synthesis? Write VHDL code for full adder by structural modeling. [8] [8] Q8) a) b) Design CMOS logic for Y = AB + CDEF. [8] Explain static & dynamic power dissipations. Give mathematical analysis. [8] Q9) Write VHDL code for FSM of Tea/Coffee vending machine. Assume suitable inputs & outputs. Also write full test bench for it. [16] Q10)Write short notes on (any three): a) I/O Block in FPGA. b) MOSFET Parasitics. c) JTAG. d) Macrocell. e) Architectural modelling. [18] EEE [3764]-1056 2

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