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1997 Course Digital System Design

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Total No. of Questions : 8] [Total No. of Pages : 3 P1460 [3764]-1092 B.E. (Computer) DIGITAL SYSTEM DESIGN (1997 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Assume suitable data, if necessary. SECTION - I Q1) a) Explain in brief the architecture of CPLD with the help of block diagram. [8] b) Write VHDL code for FSM shown in the following figure. [10] P.T.O. Q2) a) With the help of structural diagram of internal architecture explain FPGA. [8] b) Write a VHDL code full Adder. [8] Q3) a) Explain with the help of waveform Inertial Delay and Transport Delay. [8] b) Explain the different VHDL data types with the help of diagram. [8] Q4) a) Write a VHDL code for 8 : 1 MUX using CASE statement. [8] b) Explain process sensitivity list. Is it possible to write process without process sensitivity list? Justify. [8] SECTION - II Q5) a) With the help of suitable examples explain the difference between Structural, Data flow and Behavioral style of modelling. [10] b) What is the purpose of a Test Bench? Write a stimulus only test bench for D flip-flop. [8] Q6) a) Write VHDL code for 8-bit counter with an asynchronous reset input (R). The counter also has an disable input (D). On positive edge of the clock, if D = 0, the counter is incremented. If D =1, the counter holds its current value. [10] b) Explain the following VHDL code. PACKAGE Keg24_Package IS COMPONENT Keg12 PORT ( d : IN BIT_VECTOR (12, DOWN TO 0); clk : IN BIT; g : OUT BIT_VECTOR (12, DOWN TO 0); END COMPONENT; END Keg24_Package; [3764]-1092 [6] -2- Q7) a) What is the use of configuration? What is the difference between configuration specification and configuration declaration? [4] b) Explain the following attributes with suitable examples : i) S' DELAYED (T) ii) [12] S' EVENT iii) S' QUIET (T) iv) S' LAST VALUE. Q8) Write a short note on : [16] a) VHDL synthesis. b) IEEE STD_LOGIC_1164.ALL c) S' TRANSACTION Attributes. d) JTAG. rrrr [3764]-1092 -3-

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