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2003 Course VLSI Design (Elective II)

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Total No. of Questions :12] P1343 [Total No. of Pages : 3 [3764]-213 B.E. (Electrical) VLSI DESIGN (Elective - II) (2003 Course) Time :3 Hours] [Max. Marks : 100 Instructions to candidates: 1) Answer any three questions from each section. 2) Answer three questions from Section I and three questions from Section II. 3) Answers to the two sections should be written in separate books. 4) Neat diagrams must be drawn wherever necessary. 5) Figures to the right indicate full marks. 6) Assume suitable data, if necessary. SECTION - I Q1) a) b) Differentiate Mealy & Moore machine modelling along with example. [6] Implement the following : i) ii) c) m ( 0, 5, 6, 7, 9, 12 ) Using 8 : 1 Mux. [3] Implement 16 : 1 Mux using only 4 : 1 Mux [3] Draw 4 bit binary UP/DOWN asynchronous MOD 16 counter along with its timing diagram. [6] OR Q2) a) What is the need of synchronous counter? Draw Mod 6 synchronous and asynchronous counter. [6] b) Draw 4 explain 4 bit PISO shift register. [6] c) Draw state table state diagram and Implement 101 detector. [6] Define and explain in brief : [8] i) Entity. ii) Architecture. iii) Component. iv) Configuration. Draw ckt. of 2 4 decoder and write its VHDL code. [8] Q3) a) b) OR P.T.O.

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