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1997 Course VLSI Design

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Total No. of Questions : 10] P1571 [Total No. of Pages :2 [3764] - 1030 B.E. (E & T/C) VLSI DESIGN (1997 Course) Time : 3 Hours] [Max. Marks : 100 Instructions: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate answer books. 3) 4) 5) Neat diagrams must be drawn wherever necessary. Use of electronic pocket calculator is allowed. Assume suitable data, if necessary. SECTION - I Q1) a) b) Explore the architectural building blocks of FPGA in detail. List the specifications and features of any CPLD family. Q2) a) b) Draw FSM diagram and VHDL code to detect 1011 Moore sequence.[12] Compare and contrast synchronous and asynchronous sequential machines. [4] Q3) a) What the different dissipations in CMOS logic? Derive the expression for dynamic power dissipation. [8] Design CMOS logic for F= ABC +DE. Compute area on chip. [8] b) Q4) a) b) [12] [4] Staring with the operating regions of CMOS Inverter, explain voltage [8] transfer curve in detail. What is meant by power delay product? Explain in brief. [8] Q5) Write short note on any three. a) Noise margin. b) Hazards. c) Fan in. d) ASIC versus FPGA. e) Moore and Mealy machines. [18] P.T.O SECTION - II Q6) Explore high level design flow in detail. Brief every stage of design. [16] Q7) Write VHDL code for divide by 5 counter. Also write test bench for it. [16] Q8) a) b) Q9) ) b) Write VHDL code for 16 bit ALU for 6 different operations. Write full [8] test bench for it. Explore synthesis in detail. [8] What are the advance tools available for different stages in chip design. [8] What is place & route? Explain in brief. [8] Q10)Write short notes on any three. a) Attributes in VHDL. b) Delays. c) CLK skew. d) RTL. e) Functions. [18] ***** [3764] - 1030 -2-

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