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2003 Course VLSI Design

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Total No. of Questions : 12] P1517 [Total No. of Pages : 3 [3764]-224 B.E. (E & TC) VLSI DESIGN (404217) Time : 3 Hours] [Max. Marks : 100 Instructions to candidates : 1) Answer 3 questions from Section I and 3 questions from Section II. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Assume suitable data, if necessary. SECTION - I Q1) a) b) Q2) a) b) What is significance of following terms in VHDL? [8] i) Library. ii) Use. Write VHDL code & test bench for 2-input Ex-NOR gate design with minimum number(s) of 2-input NAND gate (only) as a component using structural modelling. [10] OR Explain two main processes by writing VHDL code(s) for D-Flip-Flop. What happens if VHDL designer do not assigns an output signal a value in a clocked process? [10] Write the following things in tabulated form i) Synthesiable & Non-synthesiable VHDL statements. ii) Concurrent, sequential and both concurrent plus sequential VHDL statements. [8] Q3) a) Draw FSM for (i) D-Flip Flop (ii) J-K Flip Flop and write VHDL code and test bench which will cover all state table conditions. [12] b) Explain the term Metastability with example. [4] OR Q4) Draw FSM and write VHDL code for a system which has a single bit input X and two single bit outputs Y and Z . The output of system is asserted logic 1 to Y and Z when system detects in input stream of serial bits ...... 1001.... or .... 1010 ... respectively. Comment on the hardware infered due to Gray state encoding instead of Binary state encoding in above system design. [16] P.T.O. Q5) a) b) Differentiate CPLD, FPGA & ASIC. [8] Explain antifusiable generic FPGA architecture. [8] OR Q6) a) Explain the following terms: i) LUT. ii) [4 x 2 = 8] CLB. iii) IOB. iv) Switch matrix. b) Draw generic CPLD architecture & explain its functions? [8] SECTION - II Q7) a) Write short notes on: i) SRC. ii) [3 x 3 = 9] DRC. iii) Write parasitics. b) Q8) a) b) [3764]-224 Draw circuit diagram, waveform and explain the operation of 6T SRAM cell. [9] OR Explain dynamic ROM architecture? Why NAND is prefered over NOR gate? [9] Explain with waveform that how much clock skew between CLK1 & CLK2 can be tolerated in following circuits in Fig. (8.b) when i) CLK1 is delayed after CLK2 ii) CLK2 is delayed after CLK1. [9] 2 Q9) a) b) Explain the principal and types of scaling. Explain the following terms: i) Body effect. ii) Drain punch through. iii) Hot electron. iv) CMOS parasitics. Q10)a) b) b) Q12)a) b) [4 x 2 = 8] OR Explain in detail static and dynamic power dissipation. What are main components which makes power dissipation in CMOS circuit. [8] Explain with neat legends n-well CMOS layout design rules w.r.t. i) Maximum size & ii) Minimum spacing for 1) n-well. 2) active area. 3) 4) Q11)a) poly - 1. metal - 1. [4 x 2 = 8] What do you mean by path sensitizing? Which input logic level is considered to sensitize a path through following logic gates: [8] i) AND iii) OR Explain the terms: i) Testing. iii) Validation. ii) NAND iv) NOR. [8] ii) Verification. OR Explain TAP controller with state diagram. Explain the following: i) DFT. ii) BIST. Y [3764]-224 [8] 3 [8] [8]

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